PLAY INSTRUCTIONS (ON CABINET)

Stern/Konami:  THE END
PCB PIN-OUT

Two boards (K-1100-SD and K1100-CRT)

CONTROL PANEL
 PIN - WIRE COLOR

COMPONENT SIDE (B) PIN CIRCUIT SIDE (A)

CONTROL PANEL
 PIN - WIRE COLOR

  +12V  1 -5V  
  SPEAKER   2 SPEAKER  
  3 2 Player Laser  
  2 Player Right   4 2 Player Left  
2 Player Start 5 1 Player Start
  6
  Service  7 1 Player Laser
1 Player Left  8 1 Player Right
  9
  Coin 2 10 Coin 1  
  Coin Counter 11
    12    
  Blue  13 Green  
  Sync (composite negative)  14 Red  
    15    
  GND 16 GND  
  GND 17 GND  
  +5V 18 +5V  

 

Stern/Konami:  SCRAMBLE
CONTROL PANEL PIN-OUT (12-pin)
1- White / Green- 2 PLAYER / R. BOMB   2- Yellow / Black LEFT BOMB  3- White / Brown- 1 PLAYER / R. LASER
4- White / Orange- MOVE UP   5- White / Blue LEFT LASER 6- White / Yellow MOVE RIGHT
7- White / Red MOVE DOWN  8- White / Black MOVE LEFT  9-  EMPTY
10- Green Ground   11- EMPTY 12- Green/Black GROUND

REPRO metal control panel overlays for SCRAMBLE used to be available from the link below- I don't see them now on the web site...

http://www.arcadeshop.com/parts.htm

 

STERN POWER SUPPLY INFO

Let's face it, the original power supply that came with the classic STERN games have seen better days.  I've personally had a number of them break down causing all kinds of weird symptoms- and potentially frying a PCB.  I have given up and replace them with switching power supplies. 

Arcade shop has released a plug and play solution.  Follow the link below.

http://www.arcadeshop.com/parts.htm

 

ROM SWAPS

THE END
Inserting "THE END" ROMS into a SCRAMBLE board set
results in a playable game, although the player's missile is invisible.

 

MAME ROM INFO

ROM_START( theend )
ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
ROM_LOAD( "ic13_1t.bin", 0x0000, 0x0800, 0x93e555ba )
ROM_LOAD( "ic14_2t.bin", 0x0800, 0x0800, 0x2de7ad27 )
ROM_LOAD( "ic15_3t.bin", 0x1000, 0x0800, 0x035f750b )
ROM_LOAD( "ic16_4t.bin", 0x1800, 0x0800, 0x61286b5c )
ROM_LOAD( "ic17_5t.bin", 0x2000, 0x0800, 0x434a8f68 )
ROM_LOAD( "ic18_6t.bin", 0x2800, 0x0800, 0xdc4cc786 )

ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for the audio CPU */
ROM_LOAD( "ic56_1.bin", 0x0000, 0x0800, 0x7a141f29 )
ROM_LOAD( "ic55_2.bin", 0x0800, 0x0800, 0x218497c1 )

ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
ROM_LOAD( "ic30_2c.bin", 0x0000, 0x0800, 0x68ccf7bf )
ROM_LOAD( "ic31_1c.bin", 0x0800, 0x0800, 0x4a48c999 )

ROM_REGION( 0x0020, REGION_PROMS, 0 )
ROM_LOAD( "6331-1j.86", 0x0000, 0x0020, 0x24652bc4 )
ROM_END

 

MAME CHEAT.DAT INFO

;This file can be edited with a text editor, but keep the same format:
; all fields are separated by a colon (:)
; -Name of the game (short name) [zip file or directory]
; -No of the CPU usually 0, only different in multiple CPU games
; -Address in Hexadecimal (where to poke)
; -Data to put at this address in hexadecimal (what to poke)
; -Special (see below) usually 000

; [ End, The ]
theend:0:4002:63:000:Infinite Credits
theend:0:411D:06:000:Infinite Lives
theend:0:4116:30:000:Eggs don't reappear
;Remove after initial use to advance to next level
theend:0:18DB:18:100:Invincibility
theend:0:427C:01:000:Autofire Mode "ON"

; [ End, The (Stern) ]
theends:0:4002:63:000:Infinite Credits
theends:0:411D:06:000:Infinite Lives
theends:0:4116:30:000:Eggs don't reappear
;Remove after initial use to advance to next level
theends:0:1A03:18:100:Invincibility
theends:0:427C:01:000:Autofire Mode "ON"

 

MAME HISCORE.DAT INFO

; <gamename>:
; <cpu>:<address>:<length>:<value to wait for
; in the first byte/word>:<value to wait for in the last byte/word>
; [repeat the above as many times as necessary]

theend:
theends:
0:43c0:0f:00:00  (15 BYTES - 5 HIGH SCORES - 3 BYTES EACH - REVERSE ORDER)
0:40a8:03:00:00  (TOP OF SCREEN HIGH SCORE - 3 BYTES - 1 HIGH SCORE)

REVERSE ORDER = SCORE: 12983 = ??????

LINKS

http://thelittons.net/homearcade/TheEnd/

 
IC LISTING
Top Board

IC - 2
8255
Parallel Peripheral Interface.

    Ŀ
PA3 1       40 PA4
PA2 2           39 PA5
PA1 3           38 PA6
PA0 4           37 PA7
/RD 5           36 /WR
/CE 6           35 RST
GND 7           34 D0
 A1 8           33 D1
 A0 9           32 D2
PC7 10   8255   31 D3
PC6 11          30 D4
PC5 12          29 D5
PC4 13          28 D6
PC0 14          27 D7
PC1 15          26 VCC
PC2 16          25 PB7
PC3 17          24 PB6
PB0 18          23 PB5
PB1 19          22 PB4
PB2 20          21 PB3
    





IC - 6
Z80 CPU

      Ŀ
  A11 1       40 A10
  A12 2           39 A9
  A13 3           38 A8
  A14 4           37 A7
  A15 5           36 A6
  CLK 6           35 A5
   D4 7           34 A4
   D3 8           33 A3
   D5 9           32 A2
   D6 10   Z8400  31 A1
  VCC 11    CPU   30 A0
   D2 12          29 GND
   D7 13          28 /RFSH
   D0 14          27 /M1
   D1 15          26 /RST
 /INT 16          25 /BUSRQ
 /NMI 17          24 /WAIT
/HALT 18          23 /BUSAK
/MREQ 19          22 /WR
/IORQ 20          21 /RD
      

IC - 38
8255
Parallel Peripheral Interface.

    Ŀ
PA3 1       40 PA4
PA2 2           39 PA5
PA1 3           38 PA6
PA0 4           37 PA7
/RD 5           36 /WR
/CE 6           35 RST
GND 7           34 D0
 A1 8           33 D1
 A0 9           32 D2
PC7 10   8255   31 D3
PC6 11          30 D4
PC5 12          29 D5
PC4 13          28 D6
PC0 14          27 D7
PC1 15          26 VCC
PC2 16          25 PB7
PC3 17          24 PB6
PB0 18          23 PB5
PB1 19          22 PB4
PB2 20          21 PB3
    


IC - 42
Z80 CPU

      Ŀ
  A11 1       40 A10
  A12 2           39 A9
  A13 3           38 A8
  A14 4           37 A7
  A15 5           36 A6
  CLK 6           35 A5
   D4 7           34 A4
   D3 8           33 A3
   D5 9           32 A2
   D6 10   Z8400  31 A1
  VCC 11    CPU   30 A0
   D2 12          29 GND
   D7 13          28 /RFSH
   D0 14          27 /M1
   D1 15          26 /RST
 /INT 16          25 /BUSRQ
 /NMI 17          24 /WAIT
/HALT 18          23 /BUSAK
/MREQ 19          22 /WR
/IORQ 20          21 /RD
      

 

Bottom Board

IC - 1 
74LS161

74161, 40161
4-bit synchronous binary counter with load, asynchronous reset, and ripple
carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  161  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 2 
74LS161

74161, 40161
4-bit synchronous binary counter with load, asynchronous reset, and ripple
carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  161  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 3 
M74LS10P

7410
Triple 3-input NAND gates.

    Ŀ             Ŀ       ___
 1A 1   14 VCC          A  B  C /Y   /Y = ABC
 1B 2       13 1C          ͵
 2A 3       12 /1Y          0  X  X  1 
 2B 4  7410 11 3C           1  0  X  1 
 2C 5       10 3B           1  1  0  1 
/2Y 6        9 3A           1  1  1  0 
GND 7        8 /3Y         
    

IC - 4 
M74LS139P

74139
Dual 1-of-4 inverting decoder/demultiplexer.

     Ŀ            Ŀ
/1EN 1   16 VCC        /EN S1 S0/Y0/Y1/Y2/Y3
 1S0 2       15 /2EN       ͵
 1S1 3       14 2S0         1  X  X  1  1  1  1 
/1Y0 4   74  13 2S1         0  0  0  0  1  1  1 
/1Y1 5  139  12 /2Y0        0  0  1  1  0  1  1 
/1Y2 6       11 /2Y1        0  1  0  1  1  0  1 
/1Y3 7       10 /2Y2        0  1  1  1  1  1  0 
 GND 8        9 /2Y3       
     

IC - 5 
M74LS74P

7474
Dual D flip-flop with set and reset.

      Ŀ           Ŀ
/1RST 1   14 VCC        D CLK/SET/RST Q /Q 
   1D 2       13 /2RST     ͵
 1CLK 3       12 2D         X  X   0   0  1  1 
/1SET 4  7474 11 2CLK       X  X   0   1  1  0 
   1Q 5       10 /2SET      X  X   1   0  0  1 
  /1Q 6        9 2Q         0  /   1   1  0  1 
  GND 7        8 /2Q        1  /   1   1  1  1 
                  X !/   1   1  -  - 
                             
IC - 6
M74LS377P

74377
8-bit D flip-flop with clock enable.

       Ŀ          Ŀ
/CLKEN 1   20 VCC      /CENCLK D  Q 
    Q1 2       19 Q8       ͵
    D1 3       18 D8         1  X  X  - 
    D2 4       17 D7         0  /  0  0 
    Q2 5   74  16 Q7         0  /  1  1 
    Q3 6  377  15 Q6         0 !/  X  - 
    D3 7       14 D6       
    D4 8       13 D5
    Q4 9       12 Q5
   GND 10      11 CLK
       

IC - 7
M74LS175

74175
4-bit D flip-flop with complementary outputs and reset.

     Ŀ            Ŀ
/RST 1   16 VCC        /RSTCLK D  Q /Q 
  Q1 2       15 Q4         ͵
 /Q1 3       14 /Q4          0  X  X  0  1 
  D1 4   74  13 D4           1  /  0  0  1 
  D2 5  175  12 D3           1  /  1  1  0 
 /Q2 6       11 /Q3          1 !/  X  -  - 
  Q2 7       10 Q3         
 GND 8        9 CLK
     

IC - 8
M74LS02P

7402
Quad 2-input NOR gates.

    Ŀ             Ŀ           ___
/1Y 1   14 VCC          A  B /Y       /Y = A+B
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  1 
/2Y 4  7402 11 4A           0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    

IC - 9
M74LS175

74175
4-bit D flip-flop with complementary outputs and reset.

     Ŀ            Ŀ
/RST 1   16 VCC        /RSTCLK D  Q /Q 
  Q1 2       15 Q4         ͵
 /Q1 3       14 /Q4          0  X  X  0  1 
  D1 4   74  13 D4           1  /  0  0  1 
  D2 5  175  12 D3           1  /  1  1  0 
 /Q2 6       11 /Q3          1 !/  X  -  - 
  Q2 7       10 Q3         
 GND 8        9 CLK
     


IC - 10
74LS161

74161, 40161
4-bit synchronous binary counter with load, asynchronous reset, and ripple
carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  161  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 11
74LS161

74161, 40161
4-bit synchronous binary counter with load, asynchronous reset, and ripple
carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  161  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 12 
M74LS74P

7474
Dual D flip-flop with set and reset.

      Ŀ           Ŀ
/1RST 1   14 VCC        D CLK/SET/RST Q /Q 
   1D 2       13 /2RST     ͵
 1CLK 3       12 2D         X  X   0   0  1  1 
/1SET 4  7474 11 2CLK       X  X   0   1  1  0 
   1Q 5       10 /2SET      X  X   1   0  0  1 
  /1Q 6        9 2Q         0  /   1   1  0  1 
  GND 7        8 /2Q        1  /   1   1  1  1 
                  X !/   1   1  -  - 
                             

IC - 13
M74LS139P

74139
Dual 1-of-4 inverting decoder/demultiplexer.

     Ŀ            Ŀ
/1EN 1   16 VCC        /EN S1 S0/Y0/Y1/Y2/Y3
 1S0 2       15 /2EN       ͵
 1S1 3       14 2S0         1  X  X  1  1  1  1 
/1Y0 4   74  13 2S1         0  0  0  0  1  1  1 
/1Y1 5  139  12 /2Y0        0  0  1  1  0  1  1 
/1Y2 6       11 /2Y1        0  1  0  1  1  0  1 
/1Y3 7       10 /2Y2        0  1  1  1  1  1  0 
 GND 8        9 /2Y3       
     

IC - 14
M74LS74P

7474
Dual D flip-flop with set and reset.

      Ŀ           Ŀ
/1RST 1   14 VCC        D CLK/SET/RST Q /Q 
   1D 2       13 /2RST     ͵
 1CLK 3       12 2D         X  X   0   0  1  1 
/1SET 4  7474 11 2CLK       X  X   0   1  1  0 
   1Q 5       10 /2SET      X  X   1   0  0  1 
  /1Q 6        9 2Q         0  /   1   1  0  1 
  GND 7        8 /2Q        1  /   1   1  1  1 
                  X !/   1   1  -  - 
                             
IC - 15
7432
Quad 2-input OR gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = A+B
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7432 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    

IC - 16
74163, 40163
4-bit synchronous binary counter with load, reset, and ripple carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  163  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 17
74163, 40163
4-bit synchronous binary counter with load, reset, and ripple carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  163  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 18
7420
Dual 4-input NAND gates.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  1 
 1C 4  7420 11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
                 

IC - 19
74175
4-bit D flip-flop with complementary outputs and reset.

     Ŀ            Ŀ
/RST 1   16 VCC        /RSTCLK D  Q /Q 
  Q1 2       15 Q4         ͵
 /Q1 3       14 /Q4          0  X  X  0  1 
  D1 4   74  13 D4           1  /  0  0  1 
  D2 5  175  12 D3           1  /  1  1  0 
 /Q2 6       11 /Q3          1 !/  X  -  - 
  Q2 7       10 Q3         
 GND 8        9 CLK
     

IC - 20
74194
4-bit bidirectional universal shift register with asynchronous reset
and with separate shift left and shift right serial inputs.

     Ŀ
/RST 1   16 VCC
   D 2       15 Q3
  P3 3       14 Q2
  P2 4   74  13 Q1
  P1 5  194  12 Q0
  P0 6       11 CLK
   L 7       10 S1
 GND 8        9 S0
     

IC - 21
74194
4-bit bidirectional universal shift register with asynchronous reset
and with separate shift left and shift right serial inputs.

     Ŀ
/RST 1   16 VCC
   D 2       15 Q3
  P3 3       14 Q2
  P2 4   74  13 Q1
  P1 5  194  12 Q0
  P0 6       11 CLK
   L 7       10 S1
 GND 8        9 S0
     

IC - 22
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 23
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 24
7408
Quad 2-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7408 11 4Y           0  1  0 
 2B 5       10 3B           1  0  0 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    

IC - 25
7408
Quad 2-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7408 11 4Y           0  1  0 
 2B 5       10 3B           1  0  0 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    

IC - 26
7486
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7486 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    

IC - 27
7486
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7486 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    

IC - 28
7400
Quad 2-input NAND gates.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
 2A 4  7400 11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    

IC - 29
7400
Quad 2-input NAND gates.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
 2A 4  7400 11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    

IC - 30
2716
EPROM

IC - 31
2716
EPROM

IC - 32
74194
4-bit bidirectional universal shift register with asynchronous reset
and with separate shift left and shift right serial inputs.

     Ŀ
/RST 1   16 VCC
   D 2       15 Q3
  P3 3       14 Q2
  P2 4   74  13 Q1
  P1 5  194  12 Q0
  P0 6       11 CLK
   L 7       10 S1
 GND 8        9 S0
     

IC - 33
74194
4-bit bidirectional universal shift register with asynchronous reset
and with separate shift left and shift right serial inputs.

     Ŀ
/RST 1   16 VCC
   D 2       15 Q3
  P3 3       14 Q2
  P2 4   74  13 Q1
  P1 5  194  12 Q0
  P0 6       11 CLK
   L 7       10 S1
 GND 8        9 S0
     

IC - 34
7404
Hex inverters.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  1 
/2Y 4  7404 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    

IC - 35
HM2510

IC - 36
HM2510

IC - 37
HM2510

IC - 38
HM2510

IC - 39
HM2510

IC - 40
7486
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7486 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    

IC - 41
74273

     Ŀ            Ŀ
/RST 1   20 VCC        /RSTCLK D  Q 
  1Q 2       19 8Q         ͵
  1D 3       18 8D           0  X  X  0 
  2D 4       17 7D           1  /  0  0 
  2Q 5   74  16 7Q           1  /  1  1 
  3Q 6  273  15 6Q         
  3D 7       14 6D
  4D 8       13 5D
  4Q 9       12 5Q
 GND 10      11 CLK
     

IC - 42
7430
8-input NAND gate.

    Ŀ                 ________
  A 1   14 VCC        /Y = ABCDEFGH
  B 2       13
  C 3       12 H
  D 4  7430 11 G
  E 5       10
  F 6        9
GND 7        8 /Y
    

IC - 43
7408
Quad 2-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7408 11 4Y           0  1  0 
 2B 5       10 3B           1  0  0 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    

IC - 44
7420
Dual 4-input NAND gates.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  1 
 1C 4  7420 11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
       

IC - 45
7486
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7486 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    

IC - 46
7486
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7486 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    

IC - 47







IC - 69
2114 (?)

IC - 70
2114 (?)

IC - 71
74367
2/4-bit 3-state noninverting buffer/line driver.

     Ŀ            Ŀ
/1OE 1   16 VCC        /OE A  Y 
 1A1 2       15 /2OE       ͵
 1Y1 3       14 2A2         1  X  Z 
 1A2 4   74  13 2Y2         0  0  0 
 1Y2 5  367  12 2A1         0  1  1 
 1A3 6       11 2Y1        
 1Y3 7       10 1A4
 GND 8        9 1Y4
     

IC - 72
2114 (?)

IC - 73
2114 (?)

IC - 74
74161
4-bit synchronous binary counter with load, asynchronous reset, and ripple carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  161  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     

IC - 75
M53361P

IC - 76
7474
Dual D flip-flop with set and reset.

      Ŀ           Ŀ
/1RST 1   14 VCC        D CLK/SET/RST Q /Q 
   1D 2       13 /2RST     ͵
 1CLK 3       12 2D         X  X   0   0  1  1 
/1SET 4  7474 11 2CLK       X  X   0   1  1  0 
   1Q 5       10 /2SET      X  X   1   0  0  1 
  /1Q 6        9 2Q         0  /   1   1  0  1 
  GND 7        8 /2Q        1  /   1   1  1  1 
                  X !/   1   1  -  - 
                             

IC - 77
74164
8-bit serial-in parallel-out shift register with asynchronous reset.
Gated serial inputs.

    Ŀ
 A1 1   14 VCC
 A2 2       13 QH
 QA 3   74  12 QGH
 QB 4  164  11 QF
 QC 5       10 QE
 QD 6        9 /RST
GND 7        8 CLK
    

IC - 78
74164
8-bit serial-in parallel-out shift register with asynchronous reset.
Gated serial inputs.

    Ŀ
 A1 1   14 VCC
 A2 2       13 QH
 QA 3   74  12 QGH
 QB 4  164  11 QF
 QC 5       10 QE
 QD 6        9 /RST
GND 7        8 CLK
    

IC - 79
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 80
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 81
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 82
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 83
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    

IC - 84
7402
Quad 2-input NOR gates.

    Ŀ             Ŀ           ___
/1Y 1   14 VCC          A  B /Y       /Y = A+B
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  1 
/2Y 4  7402 11 4A           0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    

IC - 85
74273

     Ŀ            Ŀ
/RST 1   20 VCC        /RSTCLK D  Q 
  1Q 2       19 8Q         ͵
  1D 3       18 8D           0  X  X  0 
  2D 4       17 7D           1  /  0  0 
  2Q 5   74  16 7Q           1  /  1  1 
  3Q 6  273  15 6Q         
  3D 7       14 6D
  4D 8       13 5D
  4Q 9       12 5Q
 GND 10      11 CLK
     

IC - 86
MM1 6331-1J
8040

IC - 87
74366
6-bit 3-state inverting buffer/line driver.

     Ŀ            Ŀ
/OE1 1   16 VCC        /OE A /Y 
  A1 2       15 /OE2       ͵
 /Y1 3       14 A6          1  X  Z 
  A2 4   74  13 /Y6         0  0  1 
 /Y2 5  366  12 A5          0  1  0 
  A3 6       11 /Y5        
 /Y3 7       10 A4
 GND 8        9 /Y4
     

IC - 88
7430
8-input NAND gate.

    Ŀ                 ________
  A 1   14 VCC        /Y = ABCDEFGH
  B 2       13
  C 3       12 H
  D 4  7430 11 G
  E 5       10
  F 6        9
GND 7        8 /Y